The first microprocessor 4004 was invented by Intel Corporation. 8085 and 8086 microprocessors were also invented by Intel. In 1981, Intel introduced an 8-bit micro-controller called the 8051. It was referred as system on a chip because it had 128 bytes of RAM, 4K byte of on-chip ROM, two timers, one serial port, and 4 ports (8-bit wide), all on a single chip. When it became widely popular, Intel allowed other manufacturers to make and market different flavors of 8051 with its code compatible with 8051. It means that if you write your program for one flavor of 8051, it will run on other flavors too, regardless of the manufacturer. This has led to several versions with different speeds and amounts of on-chip RAM.

The following table compares the features available in 8051, 8052, and 8031.

An 8051 microcontroller comes bundled with the following features −

The following illustration shows the block diagram of an 8051 microcontroller

In 8051, I/O operations are done using four ports and 40 pins. The following pin diagram shows the details of the 40 pins. I/O operation port reserves 32 pins where each port has 8 pins. The other 8 pins are designated as V_cc, GND, XTAL1, XTAL2, RST, EA (bar), ALE/PROG (bar), and PSEN (bar).

It is a 40 Pin PDIP (Plastic Dual Inline Package)

Note − In a DIP package, you can recognize the first pin and the last pin by the cut at the middle of the IC. The first pin is on the left of this cut mark and the last pin (i.e. the 40^th pin in this case) is to the right of the cut mark.

The four ports P0, P1, P2, and P3, each use 8 pins, making them 8-bit ports. Upon RESET, all the ports are configured as inputs, ready to be used as input ports. When the first 0 is written to a port, it becomes an output. To reconfigure it as an input, a 1 must be sent to a port.

It has 8 pins (32 to 39). It can be used for input or output. Unlike P1, P2, and P3 ports, we normally connect P0 to 10K-ohm pull-up resistors to use it as an input or output port being an open drain.

It is also designated as AD0-AD7, allowing it to be used as both address and data. In case of 8031 (i.e. ROMless Chip), when we need to access the external ROM, then P0 will be used for both Address and Data Bus. ALE (Pin no 31) indicates if P0 has address or data. When ALE = 0, it provides data D0-D7, but when ALE = 1, it has address A0-A7. In case no external memory connection is available, P0 must be connected externally to a 10K-ohm pull-up resistor.

MOV A,#0FFH  ;(comments: A=FFH(Hexadecimal  i.e. A=1111 1111)

It is an 8-bit port (pin 1 through 8) and can be used either as input or output. It doesn’t require pull-up resistors because they are already connected internally. Upon reset, Port 1 is configured as an input port. The following code can be used to send alternating values of 55H and AAH to Port 1.

;Toggle all bits of continuously 
MOV     A,#55 
BACK:

If Port 1 is configured to be used as an output port, then to use it as an input port again, program it by writing 1 to all of its bits as in the following code.

;Toggle all bits of continuously

Port 2 occupies a total of 8 pins (pins 21 through 28) and can be used for both input and output operations. Just as P1 (Port 1), P2 also doesn’t require external Pull-up resistors because they are already connected internally. It must be used along with P0 to provide the 16-bit address for the external memory. So it is also designated as (A0–A7), as shown in the pin diagram. When the 8051 is connected to an external memory, it provides path for upper 8-bits of 16-bits address, and it cannot be used as I/O. Upon reset, Port 2 is configured as an input port. The following code can be used to send alternating values of 55H and AAH to port 2.

;Toggle all bits of continuously 
MOV     A,#55 
BACK: 
MOV     P2,A 
ACALL   DELAY 
CPL     A         ; complement(invert) reg. A 
SJMP    BACK

If Port 2 is configured to be used as an output port, then to use it as an input port again, program it by writing 1 to all of its bits as in the following code.

;Get a byte from P2 and send it to P1 
MOV    A,#0FFH    ;A = FF hex 
MOV    P2,A       ;make P2 an input port 
BACK: 
MOV    A,P2       ;get data from P2 
MOV    P1,A       ;send it to Port 1
SJMP   BACK       ;keep doing that

It is also of 8 bits and can be used as Input/Output. This port provides some extremely important signals. P3.0 and P3.1 are RxD (Receiver) and TxD (Transmitter) respectively and are collectively used for Serial Communication. P3.2 and P3.3 pins are used for external interrupts. P3.4 and P3.5 are used for timers T0 and T1 respectively. P3.6 and P3.7 are Write (WR) and Read (RD) pins. These are active low pins, means they will be active when 0 is given to them and these are used to provide Read and Write operations to External ROM in 8031 based systems.

It is a most widely used feature of 8051 while writing code for 8051. Sometimes we need to access only 1 or 2 bits of the port instead of the entire 8-bits. 8051 provides the capability to access individual bits of the ports.

While accessing a port in a single-bit manner, we use the syntax “SETB X. Y” where X is the port number (0 to 3), and Y is a bit number (0 to 7) for data bits D0-D7 where D0 is the LSB and D7 is the MSB. For example, “SETB P1.5” sets high bit 5 of port 1.

The following code shows how we can toggle the bit P1.2 continuously.

AGAIN: 
SETB    P1.2
ACALL   DELAY    
CLR     P1.2      
ACALL   DELAY 
SJMP    AGAIN

Terms

The Program Counter is a 16- or 32-bit register which contains the address of the next instruction to be executed. The PC automatically increments to the next sequential memory location every time an instruction is fetched. Branch, jump, and interrupt operations load the Program Counter with an address other than the next sequential location.

Activating a power-on reset will cause all values in the register to be lost. It means the value of the PC (program counter) is 0 upon reset, forcing the CPU to fetch the first opcode from the ROM memory location 0000. It means we must place the first byte of upcode in ROM location 0000 because that is where the CPU expects to find the first instruction

The significance of the reset vector is that it points the processor to the memory address which contains the firmware’s first instruction. Without the Reset Vector, the processor would not know where to begin execution. Upon reset, the processor loads the Program Counter (PC) with the reset vector value from a predefined memory location. On CPU08 architecture, this is at location $FFFE:$FFFF.

When the reset vector is not necessary, developers normally take it for granted and don’t program into the final image. As a result, the processor doesn’t start up on the final product. It is a common mistake that takes place during the debug phase.

Stack is implemented in RAM and a CPU register is used to access it called SP (Stack Pointer) register. SP register is an 8-bit register and can address memory addresses of range 00h to FFh. Initially, the SP register contains value 07 to point to location 08 as the first location being used for the stack by the 8051.

When the content of a CPU register is stored in a stack, it is called a PUSH operation. When the content of a stack is stored in a CPU register, it is called a POP operation. In other words, a register is pushed onto the stack to save it and popped off the stack to retrieve it.

An infinite loop or an endless loop can be identified as a sequence of instructions in a computer program that executes endlessly in a loop, because of the following reasons −

Such infinite loops normally caused older operating systems to become unresponsive, as an infinite loop consumes all the available processor time. I/O operations waiting for user inputs are also called “infinite loops”. One possible cause of a computer “freezing” is an infinite loop; other causes include deadlock and access violations.

Embedded systems, unlike a PC, never “exit” an application. They idle through an Infinite Loop waiting for an event to take place in the form of an interrupt, or a pre-scheduled task. In order to save power, some processors enter special sleep or wait modes instead of idling through an Infinite Loop, but they will come out of this mode upon either a timer or an External Interrupt.

Interrupts are mostly hardware mechanisms that instruct the program that an event has occurred. They may occur at any time, and are therefore asynchronous to the program flow. They require special handling by the processor, and are ultimately handled by a corresponding Interrupt Service Routine (ISR). Interrupts need to be handled quickly. If you take too much time servicing an interrupt, then you may miss another interrupt.

Although numbers are always displayed in the same way, they are not stored in the same way in memory. Big-Endian machines store the most significant byte of data in the lowest memory address. A Big-Endian machine stores 0x12345678 as −

ADD+0: 0x12 
ADD+1: 0x34 
ADD+2: 0x56 
ADD+3: 0x78

Little-Endian machines, on the other hand, store the least significant byte of data in the lowest memory address. A Little-Endian machine stores 0x12345678 as −

ADD+0: 0x78 
ADD+1: 0x56 
ADD+2: 0x34 
ADD+3: 0x12

Assembly Language

Structure of Assembly Language

[ label: ]   mnemonics  [ operands ]   [;comment ]

• The label field allows the program to refer to a line of code by name. The label fields cannot exceed a certain number of characters.
• The mnemonics and operands fields together perform the real work of the program and accomplish the tasks. Statements like ADD A , C & MOV C, #68 where ADD and MOV are the mnemonics, which produce opcodes ; “A, C” and “C, #68” are operands. These two fields could contain directives. Directives do not generate machine code and are used only by the assembler, whereas instructions are translated into machine code for the CPU to execute.

1.0000         ORG  0H            ;start (origin) at location 0 
2 0000 7D25    MOV  R5,#25H       ;load 25H into R5 
3.0002 7F34    MOV  R7,#34H       ;load 34H into  R7 
4.0004 7400    MOV  A,#0          ;load 0 into A 
5.0006 2D      ADD  A,R5          ;add contents of R5 to A 
6.0007 2F      ADD  A,R7          ;add contents of R7 to A
7.0008 2412    ADD  A,#12H        ;add to A value 12 H 
8.000A 80FE    HERE: SJMP HERE    ;stay in this loop 
9.000C END                        ;end of asm source file

• The comment field begins with a semicolon which is a comment indicator.
• Notice the Label “HERE” in the program. Any label which refers to an instruction should be followed by a colon.

Assembling and Running an 8051 Program

• First, we use an editor to type in a program similar to the above program. Editors like MS-DOS EDIT program that comes with all Microsoft operating systems can be used to create or edit a program. The Editor must be able to produce an ASCII file. The “asm” extension for the source file is used by an assembler in the next step.
• The “asm” source file contains the program code created in Step 1. It is fed to an 8051 assembler. The assembler then converts the assembly language instructions into machine code instructions and produces an .obj file (object file) and a .lst file (list file). It is also called as a source file, that’s why some assemblers require that this file have the “src” extensions. The “lst” file is optional. It is very useful to the program because it lists all the opcodes and addresses as well as errors that the assemblers detected.
• Assemblers require a third step called linking. The link program takes one or more object files and produces an absolute object file with the extension “abs”.
• Next, the “abs” file is fed to a program called “OH” (object to hex converter), which creates a file with the extension “hex” that is ready to burn in to the ROM.
• 

 

Data Type

DB (Define Byte)

        ORG  500H 
DATA1:  DB   28                     ;DECIMAL (1C in hex) 
DATA2:  DB   00110101B              ;BINARY  (35 in hex) 
DATA3:  DB   39H                    ;HEX 
        ORG  510H 
DATA4:  DB   "2591"                 ;ASCII  NUMBERS 
        ORG  520H                         
DATA6:  DA   "MY NAME IS Michael"   ;ASCII CHARACTERS

Assembler Directives

• ORG (origin) − The origin directive is used to indicate the beginning of the address. It takes the numbers in hexa or decimal format. If H is provided after the number, the number is treated as hexa, otherwise decimal. The assembler converts the decimal number to hexa.
• EQU (equate) − It is used to define a constant without occupying a memory location. EQU associates a constant value with a data label so that the label appears in the program, its constant value will be substituted for the label. While executing the instruction “MOV R3, #COUNT”, the register R3 will be loaded with the value 25 (notice the # sign). The advantage of using EQU is that the programmer can change it once and the assembler will change all of its occurrences; the programmer does not have to search the entire program.
• END directive − It indicates the end of the source (asm) file. The END directive is the last line of the program; anything after the END directive is ignored by the assembler.

Labels in Assembly Language

• Each label name must be unique. The names used for labels in assembly language programming consist of alphabetic letters in both uppercase and lowercase, number 0 through 9, and special characters such as question mark (?), period (.), at the rate @, underscore (_), and dollar($).
• The first character should be in alphabetical character; it cannot be a number.
• Reserved words cannot be used as a label in the program. For example, ADD and MOV words are the reserved words, since they are instruction mnemonics.

Registers Bank/Stack

RAM Memory Space Allocation in 8051

• 32 bytes from 00H to 1FH locations are set aside for register banks and the stack.
• 16 bytes from 20H to 2FH locations are set aside for bit-addressable read/write memory.
• 80 bytes from 30H to 7FH locations are used for read and write storage; it is called as scratch pad. These 80 locations RAM are widely used for the purpose of storing data and parameters by 8051 programmers.
• 

   

Register Banks in 8051

Default Register Bank

How to Switch Register Banks

RS1	RS2	Bank Selected
0	0	Bank0
0	1	Bank1
1	0	Bank2
1	1	Bank3

Stack and its Operations

Stack in the 8051

How Stacks are Accessed

Pushing into the Stack

Popping from the Stack

Instructions

Loop and Jump Instructions

Looping in the 8051

Example

   MOV A,#0             ;A = 0,clean ACC 
   MOV R2,#10           ; the multiplier is replaced in R2 
   Add A,#25            ;add the multiplicand to the ACC

AGAIN:DJNZ R2,
AGAIN:repeat until R2 = 0 (10 times)

MOV R5 , A ;save A in R5 ;R5 (FAH)

Looping inside a Loop

• Load the accumulator with the value 55H.
• Complement the ACC 700 times.

   MOV A,#55H            ;A = 55H

NEXT

: MOV R3,#10         ;R3 the outer loop counter 
AGAIN:MOV R2,#70         ;R2 the inner loop counter

CPL A

;complement

Other Conditional Jumps

Instruction	Action
JZ	Jump if A = 0
JNZ	Jump if A ≠ 0
DJNZ	Decrement and Jump if register ≠ 0
CJNE A, data	Jump if A ≠ data
CJNE reg, #data	Jump if byte ≠ data
JC	Jump if CY = 1
JNC	Jump if CY ≠ 1
JB	Jump if bit = 1
JNB	Jump if bit = 0
JBC	Jump if bit = 1 and clear bit

• JZ (jump if A = 0) − In this instruction, the content of the accumulator is checked. If it is zero, then the 8051 jumps to the target address. JZ instruction can be used only for the accumulator, it does not apply to any other register.
• JNZ (jump if A is not equal to 0) − In this instruction, the content of the accumulator is checked to be non-zero. If it is not zero, then the 8051 jumps to the target address.
• JNC (Jump if no carry, jumps if CY = 0) − The Carry flag bit in the flag (or PSW) register is used to make the decision whether to jump or not “JNC label”. The CPU looks at the carry flag to see if it is raised (CY = 1). If it is not raised, then the CPU starts to fetch and execute instructions from the address of the label. If CY = 1, it will not jump but will execute the next instruction below JNC.
• JC (Jump if carry, jumps if CY = 1) − If CY = 1, it jumps to the target address.
• JB (jump if bit is high)
• JNB (jump if bit is low)

Unconditional Jump Instructions

• LJMP (long jump) − LJMP is 3-byte instruction in which the first byte represents opcode, and the second and third bytes represent the 16-bit address of the target location. The 2-byte target address is to allow a jump to any memory location from 0000 to FFFFH.
• SJMP (short jump) − It is a 2-byte instruction where the first byte is the opcode and the second byte is the relative address of the target location. The relative address ranges from 00H to FFH which is divided into forward and backward jumps; that is, within –128 to +127 bytes of memory relative to the address of the current PC (program counter). In case of forward jump, the target address can be within a space of 127 bytes from the current PC. In case of backward jump, the target address can be within –128 bytes from the current PC.

Calculating the Short Jump Address

Line   PC    Op-code   Mnemonic   Operand 
1      0000               ORG       0000 
2      0000  7800         MOV       R0,#003  
3      0002  7455         MOV       A,#55H0 
4      0004  6003         JZ        NEXT 
5      0006  08           INC       R0 
6      0007  04   AGAIN:  INC       A 
7      0008  04           INC       A 
8      0009  2477 NEXT:   ADD       A, #77h 
9      000B  5005         JNC       OVER 
10     000D  E4           CLR       A
11     000E  F8           MOV       R0, A 
12     000F  F9           MOV       R1, A 
13     0010  FA          MOV       R2, A 
14     0011  FB           MOV       R3, A 
15     0012  2B   OVER:   ADD       A, R3 
16     0013  50F2         JNC       AGAIN 
17     0015  80FE HERE:   SJMP      HERE 
18     0017             END

Backward Jump Target Address Calculation

CALL Instructions

LCALL (Long Call)

ACALL (Absolute Call)

Addressing Modes

• Immediate addressing mode
• Direct addressing mode
• Register direct addressing mode
• Register indirect addressing mode
• Indexed addressing mode

Immediate Addressing Mode

MOV A, #6AH

MOV A, #data

Direct Addressing Mode

MOV A, 04H

Register Direct Addressing Mode

MOV A, R4

Register Indirect Addressing Mode

MOV A, @R0

Indexed Addressing Mode

MOVC A, @A+DPTR

SFR Registers

Byte Address	Bit Address
FF
F0	F7	F6	F5	F4	F3	F2	F1	F0	B
E0	E7	E6	E5	E4	E3	E2	E1	E0	ACC
D0	D7	D6	D5	D4	D3	D2	–	D0	PSW
B8	–	–	–	BC	BB	BA	B9	B8	IP
B0	B7	B6	B5	B4	B3	B2	B1	B0	P3
A2	AF	–	–	AC	AB	AA	A9	A8	IE
A0	A7	A6	A5	A4	A3	A2	A1	A0	P2
99	Not bit Addressable								SBUF
98	9F	9E	9D	9C	9B	9A	99	98	SCON
90	97	96	95	94	93	92	91	90	P1
8D	Not bit Addressable								TH1
8C	Not bit Addressable								TH0
8B	Not bit Addressable								TL1
8A	Not bit Addressable								TL0
89	Not bit Addressable								TMOD
88	8F	8E	8D	8C	8B	8A	89	88	TCON
87	Not bit Addressable								PCON
83	Not bit Addressable								DPH
82	Not bit Addressable								DPL
81	Not bit Addressable								SP
80	87	87	85	84	83	82	81	80	P0

• A special function register can have an address between 80H to FFH. These addresses are above 80H, as the addresses from 00 to 7FH are the addresses of RAM memory inside the 8051.
• Not all the address space of 80 to FF are used by the SFR. Unused locations, 80H to FFH, are reserved and must not be used by the 8051 programmer.

CY	PSW.7	Carry Flag
AC	PSW.6	Auxiliary Carry Flag
F0	PSW.5	Flag 0 available to user for general purpose.
RS1	PSW.4	Register Bank selector bit 1
RS0	PSW.3	Register Bank selector bit 0
OV	PSW.2	Overflow Flag
–	PSW.1	User definable FLAG
P	PSW.0	Parity FLAG. Set/ cleared by hardware during instruction cycle to indicate even/odd number of 1 bit in accumulator.

CY	AC	F0	RS1	RS0	OV	–	P

RS1	RS2	Register Bank	Address
0	0	0	00H-07H
0	1	1	08H-0FH
1	0	2	10H-17H
1	1	3	18H-1FH

Timer/Counter

Difference between a Timer and a Counter

Timer	Counter
The register incremented for every machine cycle.	The register is incremented considering 1 to 0 transition at its corresponding to an external input pin (T0, T1).
Maximum count rate is 1/12 of the oscillator frequency.	Maximum count rate is 1/24 of the oscillator frequency.
A timer uses the frequency of the internal clock, and generates delay.	A counter uses an external signal to count pulses.

Timers of 8051 and their Associated Registers

Timer 0 Register

Timer 1 Register

TMOD (Timer Mode) Register

GATE

C/T (CLOCK / TIMER)

M1 / M2

M1	M2	Mode
0	0	13-bit timer mode.
0	1	16-bit timer mode.
1	0	8-bit auto reload mode.
1	1	Spilt mode.

Different Modes of Timers

Mode 0 (13-Bit Timer Mode)

Mode 1 (16-Bit Timer Mode)

Mode 2 (8 Bit Auto Reload)

Mode 3 (Split Timer Mode)

Initializing a Timer

MOV TMOD,#01h

SETB TR0

Reading a Timer

Detecting Timer Overflow

Interrupts

Hardware Interrupt

Software Interrupt

What is Polling?

Interrupts v/s Polling

Interrupt	Polling
An interrupt is like a shopkeeper. If one needs a service or product, he goes to him and apprises him of his needs. In case of interrupts, when the flags or signals are received, they notify the controller that they need to be serviced.	The polling method is like a salesperson. The salesman goes from door to door while requesting to buy a product or service. Similarly, the controller keeps monitoring the flags or signals one by one for all devices and provides service to whichever component that needs its service.

Interrupt Service Routine

Interrupt Vector Table

Interrupts	ROM Location (Hex)	Pin
Interrupts	ROM Location (HEX)
Serial COM (RI and TI)	0023
Timer 1 interrupts(TF1)	001B
External HW interrupt 1 (INT1)	0013	P3.3 (13)
External HW interrupt 0 (INT0)	0003	P3.2 (12)
Timer 0 (TF0)	000B
Reset	0000	9

• When the reset pin is activated, the 8051 jumps to the address location 0000. This is power-up reset.
• Two interrupts are set aside for the timers: one for timer 0 and one for timer 1. Memory locations are 000BH and 001BH respectively in the interrupt vector table.
• Two interrupts are set aside for hardware external interrupts. Pin no. 12 and Pin no. 13 in Port 3 are for the external hardware interrupts INT0 and INT1, respectively. Memory locations are 0003H and 0013H respectively in the interrupt vector table.
• Serial communication has a single interrupt that belongs to both receive and transmit. Memory location 0023H belongs to this interrupt.

Steps to Execute an Interrupt

• The microcontroller closes the currently executing instruction and saves the address of the next instruction (PC) on the stack.
• It also saves the current status of all the interrupts internally (i.e., not on the stack).
• It jumps to the memory location of the interrupt vector table that holds the address of the interrupts service routine.
• The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it. It starts to execute the interrupt service subroutine, which is RETI (return from interrupt).
• Upon executing the RETI instruction, the microcontroller returns to the location where it was interrupted. First, it gets the program counter (PC) address from the stack by popping the top bytes of the stack into the PC. Then, it start to execute from that address.

Edge Triggering vs. Level Triggering

Level Triggered	Edge Triggered
A level-triggered interrupt module always generates an interrupt whenever the level of the interrupt source is asserted.	An edge-triggered interrupt module generates an interrupt only when it detects an asserting edge of the interrupt source. The edge gets detected when the interrupt source level actually changes. It can also be detected by periodic sampling and detecting an asserted level when the previous sample was de-asserted.
If the interrupt source is still asserted when the firmware interrupt handler handles the interrupt, the interrupt module will regenerate the interrupt, causing the interrupt handler to be invoked again.	Edge-triggered interrupt modules can be acted immediately, no matter how the interrupt source behaves.
Level-triggered interrupts are cumbersome for firmware.	Edge-triggered interrupts keep the firmware’s code complexity low, reduce the number of conditions for firmware, and provide more flexibility when interrupts are handled.

Enabling and Disabling an Interrupt

Interrupt Enable Register

EA	–	ET2	ES	ET1	EX1	ET0	EX0

• EA − Global enable/disable.
• – − Undefined.
• ET2 − Enable Timer 2 interrupt.
• ES − Enable Serial port interrupt.
• ET1 − Enable Timer 1 interrupt.
• EX1 − Enable External 1 interrupt.
• ET0 − Enable Timer 0 interrupt.
• EX0 − Enable External 0 interrupt.

• Bit D7 of the IE register (EA) must be high to allow the rest of register to take effect.
• If EA = 1, interrupts will be enabled and will be responded to, if their corresponding bits in IE are high. If EA = 0, no interrupts will respond, even if their associated pins in the IE register are high.

Interrupt Priority in 8051

–	–	–	–	PT1	PX1	PT0	PX0

–	IP.7	Not Implemented.
–	IP.6	Not Implemented.
–	IP.5	Not Implemented.
–	IP.4	Not Implemented.
PT1	IP.3	Defines the Timer 1 interrupt priority level.
PX1	IP.2	Defines the External Interrupt 1 priority level.
PT0	IP.1	Defines the Timer 0 interrupt priority level.
PX0	IP.0	Defines the External Interrupt 0 priority level.

Interrupt inside Interrupt

Triggering an Interrupt by Software